1. Field of the Invention
The present invention relates to a high speed data transfer apparatus for duplexing in an ATM (Asynchronous Transfer Mode) switching system.
2. Discussion of Related Art
In general, there should be provided a fault tolerance function and a real time process function in the electronic switching system, unlike conventional computer systems. Further, reliability and solubility are very necessary to the electronic switching system a down time of which should be less several minutes for 1 year. The solubility means a possibility of permitting the system to normally perform its original operation at any time. And, the fault tolerance function of the system is subjected to employ a duplex method. The duplex method is composed of the same systems, one of which is an active mode system and the other of which is a standby mode system. Therefore, under use, if a fault is found in the active mode system, the standby mode system is employed to perform a series of operations which have been executed by the active mode system. As a result, the duplex method does not permit the system to have such a fault.
FIG. 1 is a schematic construction diagram of a high speed data transfer channel capable of performing a concurrent writing in an electronic switching system TDX-10 according to the prior art.
Referring to FIG. 1, active/standby mode systems are shown therein and only the system which is under operation can be the active mode system. After the system is determined as the active or the standby mode system, only the processor of the active mode system can access resources of the standby mode system.
Main processor and memory management board assemblies 1 and 1' (hereinafter, called them MPMA) are used as main processors having the CPU (central processing unit) and a memory. Mass storage interface board assemblies 2 and 2' (hereinafter, called them MSIA) are used for managing auxiliary storage units like disk and MT. I/O interface board assemblies 5 and 5' (hereinafter, called them IOIA) are used as a kind of multiplexer to manage an input/output interface. Memory and error correction board assemblies 3 and 3' (hereinafter, called them MECA) are used as memory expansion boards. Duplication control channel board assemblies 4 and 4' (hereinafter, called them DCCA) are used for providing the high speed data transfer channel between the duplex processors.
The Duplex modes, i.e., the active and standby mode systems are subjected to each having their power and their buses separated from each other. And, in their operations, when the MPMA 1 of the active mode system writes data in its own local memory or the MECA 3, the high speed data transfer channel of the TDX-10 permits the DCCA board 4 of the active mode system to write corresponding data in the MECA 3' or the MPMA 1' of the standby mode system through the high speed data transfer channel UP-bus.
At this time, a response to the writing operation in the active mode system is delayed until another response is received from the standby mode system. Thereby, the high speed data transfer channel of the TDX-10 can not perform the next operation until one writing operation is completed in the standby mode system and its response is then received. This has caused reduction in the system's capability.